1. Technical Field
The present disclosure relates to a synchronous memory device and, more particularly to a synchronous memory device having improved operational characteristics.
2. Discussion of Related Art
A synchronous memory device inputs and outputs data in synchronization with external clock signals. Since the external interface of a synchronous memory device is synchronized with an external clock signal, a controller can preset a clock cycle at which valid data can be output after the issuance of a read command.
In general, Column Access Strobe (CAS) latency is the time from the point at which a read command is applied to a synchronous memory device to the point at which data is output which is represented using a multiple of an external clock signal cycle tCC. That is, data is output from a synchronous memory device after a certain number of clock cycles corresponding to the CAS latency after the reception of the read command (or a column address applied along with the read command). For example, if the CAS latency is five, data must be output five cycles after the external clock cycle when the read command was applied.
FIG. 1 is a block diagram illustrating a conventional synchronous memory device.
Referring to FIG. 1, the conventional synchronous memory device 1 includes a memory cell array 10, a data output buffer 20, a clock recovery circuit 30, a replica circuit 40, a read command buffer 50, a clock delay circuit 70, a mode register 80, and a latency circuit 90.
When a read command READ CMD is provided to the synchronous memory device 1, data DATA is output from the memory cell array 10 corresponding to an externally-provided address ADDRESS. The data output buffer 20 outputs the data DATA received from the memory cell array 10 in response to a latency signal LATENCY and a data output clock signal CLKDQ. The data output buffer 20 of the synchronous memory device 1 is triggered by the data output clock signal CLKDQ, and outputs data only when the latency signal LATENCY has been enabled.
The clock recovery circuit 30 shown by a dashed box in FIG. 1 includes a phase detector 32 and a variable-delay unit 34, and provides the data output clock signal CLKDQ in response to an external clock signal ECLK and a feedback clock signal CLKF. The replica circuit 40 provides the feedback clock signal CLKF whose time difference with respect to the data output clock signal CLKDQ is substantially identical to the time period tSAC that it takes the data output buffer 20 to output data received from the memory cell array 10 in response to the data output clock signal CLKDQ.
The read command buffer 50 provides an internal read signal PREAD after a delay of a predetermined time TREAD in response to the external clock signal ECLK and the read command READ CMD. The clock delay circuit 70 receives the data output clock signal CLKDQ and provides a plurality of transfer signals TR1, TR2, TR3 and TR4 having predetermined time differences with respect to the data output clock signal CLKDQ. The mode register 80 stores an external mode register set command MRS CMD. In this case, the mode register set command MRS CMD represents the mode of the synchronous memory device 1. The CAS latency CLi, where “i” is an integer, is determined by the mode register set command MRS CMD.
The latency circuit 90 receives the internal read signal PREAD, and provides latency signals LATENCY delayed by predetermined times, corresponding to the CAS latency CLi, with respect to the internal read signal PREAD in response to the transfer signals TR1, TR2, TR3 and TR4. In general, when the first transfer signal TR1 is provided to the latency circuit 90 at substantially the same time as the internal read signal PREAD, ft is possible to precisely sample the internal read signal PREAD.
In the conventional synchronous memory device 1, a predetermined time TREAD after which the read command READ CMD is input from the outside, and before which the internal read signal PREAD is provided to the latency circuit 90, can not be precisely determined. Furthermore, since the point at which the internal read signal PREAD is provided varies depending on process variables, such as Process, Voltage and Temperature (PVT), the points at which the transfer signals TR1, TR2, TR3 and TR4 are provided from the clock delay circuit 70 to the latency circuit 90 must be designed to have a timing margin in consideration of such variation. Since the timing margin decreases as the frequency of the external clock signal ECLK increases, it is difficult to design the transfer signals TR1, TR2, TR3 and TR4 to be provided at precise times through simulation.